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| - | ====== DRIE Si Etch Recipes ====== | ||
| - | We use DRIE silicon etches for assorted processes while making microrobots. The processes use different procedures depending on the etch depth. | ||
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| - | ===== Shallow DRIE Etch ===== | ||
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| - | For Si etching down to perhaps 40um deep. | ||
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| - | Typically, we deposit 2um MiR 701 photoresist on top of silicon, then use on the order of 60 cycles of the standard sts2 deep silicon etch. DRIE photoresist vs. silicon etch selectivity is around 1:50 or 1:100 (it varies). | ||
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| - | ==== Process Notes ==== | ||
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| - | ^ Date ^ Person ^ Data ^ | ||
| - | | 20 July 2021 | Daniel | Hard baked with recipe U on axcelis. 50 cycles HF etch -> 20um depth, 25 more cycles HF -> 30um depth, 25 cycles LF -> 40um depth in large areas. | | ||
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| - | ===== Deep DRIE Etch ===== | ||
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| - | Deeper etches need a thicker mask material. DRIE photoresist vs. silicon etch selectivity is around 1:50 or 1:100 (it varies), so a 550um through-wafer etch needs at least 10um photoresist. SiO2 vs. Si selectivity is also around 1:100 but reliably higher than photoresist selectivity (but not enough to justify the extra steps required to deposit 5um+ oxide), and metal selectivity is near-infinite (but metal masks are not allowed in sts2 as the metal sputters off and contaminates the chamber, which is not good for a tool shared by multiple projects). | ||
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| - | The solution is to use a very thick photoresist. Unfortuately, | ||
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| - | Previously, we've used 12um AZ P4620 resist hard baked at 120C for one hour. Also, etches with less than 100um of Si thickness remaining require a handle wafer in the sts2 tool. | ||
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| - | ==== Process Notes ==== | ||
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| - | ^ Date ^ Person ^ Data ^ | ||
| - | | 16 Nov 2021 | Daniel | Talked to Ryan and Allison in the NanoLab. The NanoLab switched to AZ P4620 thick resist (instead of SPR 220) because the SPR 220 can cause cracks around the edge of Si wafers, which then shatter in the sts2 chamber. AZ P4620 does not expose as well, but it does not cause this cracking and has different failure modes; the switch has significantly decreased (10x?) the wafer shattering rate. | | ||
recipe-drie.1637105656.txt.gz ยท Last modified: 2021/11/16 15:34 by dteal
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