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--- soi-process [2021/07/28 19:55]
dteal
+++ soi-process [2022/05/16 16:26] (current)
dteal
@@ Line 12: / Line 12: @@
 ===== Frontside Metal =====
+  * 2um minimum feature size
+  * must be at least 5um from frontside etches to avoid exposure during frontside DRIE
 We start by patterning metal on the frontside via liftoff to improve wirebonding and make contact with micromanipulator probes easier (also, for silver epoxy to make an electrical connection to the gold; it doesn't form an ohmic contact to the silicon).
-Thickness is typically 300 to 500nm of Cr (as an adhesion layer) then Au (for conductivity and preventing oxidation). Current designs are robust to metal variations.
+Thickness is typically 100 to 300nm of Cr (as an adhesion layer) then Au (for conductivity and preventing oxidation). Current designs are robust to metal variations.
 See the [[recipe-liftoff|liftoff recipe page]] for current best practices.
@@ Line 21: / Line 24: @@
 ===== Frontside Silicon =====
-Next, we DRIE etch the 40um frontside layer to produce inchworm motors and other MEMS structures using the buried oxide as an etch stop. We typically achieve a 2um minimum feature size. Our inchworm motors are fairly robust to sidewall geometry (DRIE scallop size, draft angle, and overetch). It's important for the DRIE etch mask to completely cover the metal layer to avoid exposure to the DRIE etch (which could sputter the metal to contaminate the etch chamber).
+  * 2um minimum feature size, but use 3um to be safe
+  * up to 30% of pattern area may be etched
+  * etched areas must be at least 5um from the metal layer to avoid metal exposure during frontside DRIE
+  * after the HF release etch, 10um features are released, 50um+ features are anchors.
-See the [[recipe-DRIE|DRIE silicon etch page]] for current best practices.
+Next, we DRIE etch the 40um frontside layer to produce inchworm motors and other MEMS structures using the buried oxide as an etch stop. We typically achieve around a 2um minimum feature size, though it is wise to design for minimum feature sizes of 3um or more in case of process variation. Our inchworm motors are fairly robust to sidewall geometry (DRIE scallop size, draft angle, and overetch). It's important for the DRIE etch mask to completely cover the metal layer to avoid exposure to the DRIE etch (which could sputter the metal to contaminate the etch chamber).
+To avoid etch gas depletion, we've traditionally had a design rule that at most 30% of exposed frontside silicon can be etched.
+For etch holes for the vapor HF release, we typically use 8x8um squares on a 14x14um square grid.
+See the [[sts2|sts2 DRIE silicon etch page]] for current best practices.
 ===== Backside Silicon =====
-TODO
+  * either 40um exact feature size or 200um minimum feature size, depending on the fabrication run
+  * up to 30% of pattern area may be etched
+  * there may be tens of offset between frontside and backside edges
+After completing the frontside features, we DRIE etch a pattern through the backside to dice the chips into assorted shapes. Depending on the process, we usually use exactly 40um wide features (no more, no less), or a 200um minimum feature size. We take the following major effects into consideration:
+  - The backside is never perfectly aligned to the frontside. This misalignment is probably less than 10um.
+  - A DRIE etch, unless perfectly tuned, does not have perfectly perpendicular sidewalls. We usually operate with the conservative assumption that sidewall angle is within 1 degree of perpendicular. This means that, for a 550um deep etch, the bottom of the etch might end up offset by tan(1deg)*550um = 10um. In other words, a 40um wide feature might become 40+(10*2)=60um wide at the bottom of the etch.
+  - Finally, a DRIE etch will vary its etch rate with pattern geometry ("aspect ratio dependent etch", "ARDE") mainly because very narrow features have less etching plasma/gas flow. As a result, when the etch is run to completion, features with much larger exposed area will etch faster, then experience overetch. If this overetch is too high, it might break through the buried oxide layer to the frontside. Extra etch gases might begin to significantly etch frontside features. This is bad.
+Because of (1) and (2), it makes sense to have a minimum backside feature size somewhere around 40um. Because of (3), it makes sense for all the geometry to either be the exact same size or for all features to be large enough that ARDE is negligible. Thus our two common processes are as previously described: all features are 40um wide trenches, or all features are at least 200um wide.
+Note that (1) and (2) also imply there can be tens of microns of offset between the frontside and the edge of backside patterns.
+===== Vapor HF Release =====
+As a final step, we run a timed HF etch on primaxx to etch at least 5um buried oxide. This means frontside silicon structures less than 10um wide will be released. Frontside structures should be at least 50um wide (to have some error room) to remain anchored.
+===== Layout Files =====
+{{ :bamlab_40umtrench_layers.lyp |}}
 ^ Date ^ Person ^ Data ^
 | (date) | Daniel | (notes) |

Berkeley Autonomous Microsystems Lab

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