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--- sts2 [2021/02/10 00:04]
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+++ sts2 [2021/11/18 14:40] (current)
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 {{sts2.jpg?0x200 |picture of sts2 and sts-oxide tools}}
-===== Process Notes =====
+===== Etch Recipes =====
+==== Shallow DRIE Etch ====
+For Si etching down to perhaps 40um deep.
+Typically, we deposit 2um MiR 701 photoresist (see [[mla150|mla150 data]]) on top of silicon, hardbake in axcelis (recipe U), then use on the order of 60 cycles of the standard sts2 deep silicon etch. DRIE photoresist vs. silicon etch selectivity is around 1:50 or 1:100 (it varies).
+^ Date ^ Person ^ Data ^
+| 20 July 2021 | Daniel | Hard baked with recipe U on axcelis. 50 cycles HF etch -> 20um depth, 25 more cycles HF -> 30um depth, 25 cycles LF -> 40um depth in large areas. |
+==== Deep DRIE Etch ====
+Deeper etches need a thicker mask material. DRIE photoresist vs. silicon etch selectivity is around 1:50 or 1:100 (it varies), so a 550um through-wafer etch needs at least 10um photoresist. SiO2 vs. Si selectivity is also around 1:100 but reliably higher than photoresist selectivity (but not enough to justify the extra steps required to deposit 5um+ oxide), and metal selectivity is near-infinite (but metal masks are not allowed in sts2 as the metal sputters off and contaminates the chamber, which is not good for a tool shared by multiple projects).
+The solution is to use a very thick photoresist. Unfortuately, thick photoresists have multiple problems. DNQ-based photoresists (i.e., most positive photoresists) require some water in the resist.
+Previously, we've used 12um AZ P4620 resist hard baked at 120C for one hour. Also, etches with less than 100um of Si thickness remaining require a handle wafer in the sts2 tool.
+^ Date ^ Person ^ Data ^
+| 16 Nov 2021 | Daniel | Talked to Ryan and Allison in the NanoLab. The NanoLab switched to AZ P4620 thick resist (instead of SPR 220) because the SPR 220 can cause cracks around the edge of Si wafers, which then shatter in the sts2 chamber. AZ P4620 does not expose as well, but it does not cause this cracking and has different failure modes; the switch has significantly decreased (10x?) the wafer shattering rate. |
+====== Tool-Specific Effects ======
+Some edge cases for processes on sts2 result in weird effects.
 ^ Date ^ Person ^ Data ^
-| 11 Jan 2021 | Daniel | Etching the entire surface of a 6" silicon wafer with the standard deep silicon recipe leaves thick sulfer dust on top of the wafer! Apparently, the overabundance of silicon means more fluorine leaves the etch as SiF4 and there is not enough fluorine left to carry the sulfer away in a gaseous state. The solution is to increase the SF6 and O2 flow rates during the etch (from 130/30 to 260/26 or something). |
+| 11 Jan 2021 | Daniel | Etching the entire surface of a 6" silicon wafer with the standard deep silicon recipe leaves thick sulfer dust and/or silicon grass on top of the wafer! According to Ryan Rivers, the overabundance of silicon means more fluorine leaves the etch as SiF4 and there is not enough fluorine left to carry the sulfer away in a gaseous state. The solution is to increase the SF6 and O2 flow rates during the etch (from 130/30 to 260/26 or something). |
 | 18 Jan 2021 | Daniel | On the other hand, if almost the entire wafer surface is masked by photoresist, some of the activated neutrals in the plasma appear to be able to make their way around the edge of the wafer and make a very minor etch in a ring where the wafer sits on the edge of the platen. |

Berkeley Autonomous Microsystems Lab

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